The present invention relates generally to semiconductor fabrication and, more particularly to a method for measuring alignment marks in semiconductor fabrication.
The use of alignment marks to measure and control the overlay accuracy of various layers in semiconductor processing is well known. Traditionally, optical detection and measurement of the alignment marks has been employed. A top layer is aligned to underlying layers by detecting the overlay variation between an alignment feature that has previously been formed on the underlying layer(s) and an alignment feature that is formed in a photoresist layer on the top layer. Oftentimes a box in a box pattern is employed, such as illustrated in FIG. 1a, with one box having been formed in the underlying layer and the other box having been formed in the resist layer.
As device geometries and features sizes decrease, alignment of the layers becomes increasingly critical and tolerances become increasingly tighter. Unfortunately, as device geometries and feature sizes decrease, detection and measurement of the alignment marks becomes more difficult. One reason for this difficulty is that resist lines are transparent and have very small vertical dimensions. Generally, if the height of features defined by the resist Ones is more than one fourth of the illuminating light wavelength (xcex/4) of the conventional optical methods, the features are easily visible due to destructive interference of the light between the top and bottom surface of the features. As device geometries shrink, and the height of the alignment features decreases below xcex/4, visibility of the features diminishes due to loss of contrast Thus, the alignment features cannot be effectively utilized. Furthermore, the resist features; which are typically transparent at the illuminating light source wavelengths, are particularly difficult to see on polished silicon wafers.
What is needed then is a method and apparatus for detecting and measuring alignment features that have a height less than one fourth the illuminating light source wavelength and that can be easily integrated as an adjunct method and apparatus used with conventional alignment techniques. The method must also allow visibility of resist lines on polished (i.e. highly reflective) surfaces, such as a silicon wafer or metal layers including but not limited to aluminum, copper, or tungsten.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by the present invention that provides for a structure having a method for overlay metrology of low contrast alignment features.
In a first aspect, the present invention provides for a method of detecting the alignment of two layers in an integrated circuit comprised of multiple stacked layers of material, one underlying layer having a first alignment mark and one overlying layer having a second alignment mark. The method comprises detecting the first alignment mark and a reference alignment mark using a first alignment tool and forming thereof a first image and detecting the second alignment mark and the reference alignment mark using a second alignment tool and forming thereof a second image. The method further comprises forming a composite image from the first and second image by aligning the reference mark in the first and second image.
In another aspect, the invention provides for an alignment detection apparatus comprising a stage having a surface for receiving thereon a semiconductor wafer, a light source directed to illuminate a wafer when placed upon said stage, and a beam splitter located to intercept light from said light source reflected off a wafer placed upon said stage and to split said reflected light into a first light path and a second light path. The apparatus further includes an optical tool in the first light path and a wavefront sensing tool in the second light path. The apparatus further comprises a computer coupled to the optical tool and the wavefront sensing tool and receiving there from alignment detection data and outputting an alignment image.
In yet another aspect, the invention provides for a method for measuring the overlay alignment of at least two layers of a semiconductor device using a wavefront sensing tool. The method includes generating a reference signal by observing a flat reference surface with the wavefront sensing tool and storing the resulting signal, aligning at least a portion of the semiconductor wafer containing a first and second alignment mark with the wavefront sensing tool, and illuminating the portion of the wafer and detecting a wavefront of light reflected from the portion of the wafer and from the first and second alignment marks. The method further includes magnifying the reflected wavefront of light, generating a wavefront slope signal by observing the magnified reflected wavefront of light with the wavefront sensing tool, determining the location of the first and second alignment marks by comparing the wavefront slope signal with the reference signal, and calculating a distance between the first and second alignment marks based upon the results of the step of determining the location of the first and second alignment marks.
An advantage of the preferred embodiment of the present invention is that is can be used as an adjunct method to existing metrology techniques.
Another advantage of the preferred embodiment of the present invention is that the measurement data can be easily combined with the data of other metrology techniques.
Yet another advantage of a preferred embodiment of the present invention is that it can be easily interfaced with a computer system for viewing and analysis.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention wilt be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.